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data sheet ?2008 cadeka microcircuits llc www.cadeka.com CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a CDK1305 10-bit, 40 msps 175mw a/d converter ampl i f y t h e h uman exp eri e n c e features n 40 msps converter n 175mw power dissipation n on-chip track-and-hold n single +5v power supply n ttl/cmos outputs n 5pf input capacitance n tri-state output buffers n high esd protection: 3,500v minimum n selectable +3v or +5v logic i/o a pplications n all high-speed applications where low power dissipation is required n video imaging n medical imaging n radar receivers n ir imaging n digital communications general description the CDK1305 is a 10-bit, low power analog-to-digital converter capable of minimum word rates of 40 msps. the on-chip track-and-hold function assures very good dynamic performance without the need for external components. the input drive requirements are minimized due to the cdk130 5 low input capacitance of only 5pf. power dissipation is extremely low at only 175mw typical at 40 msps with a power supply of +5.0v. the digital outputs are +3v or +5v, and are user selectable. the CDK1305 is pin-compatible with an entire family of 10-bit, cmos converters (cdk1304/05/06), which simplifes upgrades. the CDK1305 has incorporated proprietary circuit design* and cmos processing technologies to achieve its advanced performance. inputs and outputs are ttl/cmos-compatible to interface with ttl/cmos logic systems. output data format is straight binary. the CDK1305 is available in 28-lead soic and 32-lead small (7mm square) tqfp packages over the commercial temperature range. block diagram ordering information part number package pb-free rohs compliant operating temperature range packaging method CDK1305cso28 soic-28 yes yes 0c to +70c rail CDK1305cso28_q soic-28 no no 0c to +70c rail CDK1305ctq32 tqfp-32 yes yes 0c to +70c rail CDK1305ctq32_q tqfp-32 no no 0c to +70c rail moisture sensitivity level for soic-28 is msl-1 and tqfp is msl-3.
?2008 cadeka microcircuits llc www.cadeka.com 2 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a pin confguration soic-28 tqfp-32 pin assignments soic-28 tqfp-32 pin name description 1,8 3,4,28,29 agnd analog ground 2 30 v rhf reference high force 3 31 v rhs reference high sense 5 32 v rls reference low sense 6 1 v rlf reference low force 9 5 v cal calibration reference 7 2 v in analog input 10 6,7 av dd analog v dd 11 8,9 dv dd digital v dd 12 10,11 dgnd digital ground 13 12 clk input clock ? clk = fs (ttl) 15 14 en output enable 16-20, 23-27 15-19, 22-26 d0-d9 tri-state data output, (d0 = lsb) 28 27 d10 tri-state output overrange 14 13 d av data valid output 22 21 ov dd digital output supply 21 20 ognd digital output ground 4 C n/c no connect CDK1305 CDK1305
?2008 cadeka microcircuits llc www.cadeka.com 3 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a absolute maximum ratings the safety of the device is not guaranteed when it is operated above the absolute maximum ratings. the device should not be operated at these absolute limits. adhere to the recommended operating conditions for proper de - vice function. the information contained in the electrical characteristics tables and typical performance plots refect the operating conditions noted on the tables and plots. parameter min max unit supply voltages av dd +6 v dv dd +6 v input voltages analog input -0.5 av dd +0.5 v v ref 0 av dd v clk input v dd v av dd C dv dd -100 100 mv agnd C dgnd -100 100 mv digital outputs 10 ma reliability information parameter min typ max unit storage temperature range -65 +150 c recommended operating conditions parameter min typ max unit operating temperature range 0 +70 c junction temperature range +175 c lead temperature (soldering 10 seconds) +300 c
?2008 cadeka microcircuits llc www.cadeka.com 4 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a electrical characteristics (t a = t min to t max , av dd = dv dd = ov dd = +5v, v in = 0 to 4v, ? clk = 40 msps, v rhs = 4v, v rls = 0v; unless otherwise noted) symbol parameter conditions min typ max units resolution 10 bits dc performance dle differential linearity error (1) -0.5 +0.5 lsb ile integral linearity error (1) -1.0 +1.0 lsb no missing codes guaranteed analog input input voltage range (1) v rls v rhs v input resistance (2) 50 k input capacitance 5 pf input bandwidth small signal 250 mhz gain error 2.0 lsb offset error 2.0 lsb reference input resistance (1) 300 500 600 bandwidth small signal 150 mhz voltage range v rls (2) 0 2.0 v v rhs (2) 3.0 av dd v v rhs C v rls 4.0 v (v rhf C v rhs ) 90 mv (v rls C v rlf ) 75 mv reference settling time v rhs 15 clk cycle v rls 20 clk cycle conversion characteristics maximum conversion rate (1) 40 mhz minimum conversion rate (2) 2 mhz pipeline delay (latency) (2) 12 clk cycle aperture delay time 4.0 ns aperture jitter time 30 ps pp dynamic performance enob effective number of bits ? in = 3.58mhz 8.5 bits ? in = 10.3mhz 8.3 bits snr signal-to-noise ratio w/o harmonics ? in = 3.58mhz (1) 52 54 db ? in = 10.3mhz (1) 51 52 db thd total harmonic distortion ? in = 3.58mhz (1) , 9 distortion bins from 1024 pt fft 55 61 db ? in = 10.3mhz (1) , 9 distortion bins from 1024 pt fft 52 53 db sinad signal-to-noise and distortion ? in = 3.58mhz (1) 51 54 db ? in = 10.3mhz (1) 49 52 db notes: 1. 100% production tested at +25c. 2. parameter is guaranteed (but not tested) by design and characterization data.
?2008 cadeka microcircuits llc www.cadeka.com 5 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a electrical characteristics (t a = t min to t max , av dd = dv dd = ov dd = +5v, v in = 0 to 4v, ? clk = 40 msps, v rhs = 4v, v rls = 0v; unless otherwise noted) symbol parameter conditions min typ max units sfdr spurious free dynamic range ? in = 1mhz 63 ps pp differential phase 0.3 deg differential gain 0.3 % digital inputs logic 1 voltage (1) 2.0 v logic 0 voltage (1) 0.8 v maximum input current low (1) -10 +10 a maximum input current high (1) -10 +10 a input capacitance +5 pf digital outputs logic 1 voltage (1) i oh = 0.5ma 3.5 v logic 0 voltage (1) i ol = 1.6ma 0.4 v t r rise time 15pf load 10 ns t f fall time 15pf load 10 ns output enable to data output delay 20pf load, t a = 25c 10 ns 50pf load over temp 22 ns power supply requirements ov dd digital voltage supply (2) 3.0 5.0 v dv dd 4.75 5.0 5.25 v av dd 4.75 5.0 5.25 v ai dd digital voltage current (1) 17 22 ma di dd 18 23 ma power dissipation (1) 175 225 mw notes: 1. 100% production tested at +25c. 2. parameter is guaranteed (but not tested) by design and characterization data.
?2008 cadeka microcircuits llc www.cadeka.com 6 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a typical performance characteristics (t a = t min to t max , av dd = dv dd = ov dd = +5v, v in = 0 to 4v, ? clk = 40 msps, v rhs = 4v, v rls = 0v; unless otherwise noted) p erformance vs. sample rate snr, thd, sina d vs. input freq. snr, t hd vs. input range p ower dissipation vs. sample rate spectral response p erformance vs. temperature 63 performance (db) 54 55 56 57 58 59 60 61 62 0 5 10 15 20 25 30 35 40 sample rate (msps) ? in = 1mhz thd snr sinad 80 snr, thd, sinad (db) 10 20 30 40 50 60 70 0 10 100 1000 input frequency (mhz) thd snr sinad 70 snr, thd (db) 0 10 20 30 40 50 60 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 input range (v) thd snr ? in = 1mhz ? s = 40 msps 220 200 total power (mv) 60 80 100 120 140 160 180 10 15 20 25 30 35 40 45 sample rate (msps) v in = 4v sinewave v in = 0v 0 amplitude (db) -120 -90 -60 -30 0 1 2 3 4 5 6 7 8 9 10 input frequency (mhz) ? in = 1.035mhz ? s = 40 msps 62 performance (db) 50 52 54 56 58 60 -40 -20 0 20 40 60 80 100 temperature (c) ? in = 1mhz ? s = 40 msps thd snr sinad
?2008 cadeka microcircuits llc www.cadeka.com 7 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a specifcation defnitions a perture delay aperture delay represents the point in time, relative to the rising edge of the clock input, that the analog input is sampled. a perture jitter the variations in aperture delay for successive samples. differential gain (dg) a signal consisting of a sine wave superimposed on vari - ous dc levels is applied to the input. differential gain is the maximum variation in the sampled sine wave ampli - tudes at these dc levels. differential p hase (dp) a signal consisting of a sine wave superimposed on vari - ous dc levels is applied to the input. differential phase is the maximum variation in the sampled sine wave phases at these dc levels. effective number o f bits (enob) sinad = 6.02n + 1.76, where n is equal to the effective number of bits. n = sinad C 1.76 6.02 i nput bandwidth small signal (50mv) bandwidth (3db) of analog input stage. differential linearity e rror (dle) error in the width of each code from its theoretical value. (theoretical = v fs /2 n ) integral linearity e rror (ile) linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from Cfs through +fs. the deviation is measured from the edge of each particular code to the true straight line. o utput delay time between the clocks triggering edge and output data valid. overvoltage recovery time the time required for the adc to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. signal-to-noise r atio (snr) the ratio of the fundamental sinusoid power to the total noise power. harmonics are excluded. signal-to-noise a nd distortion (sinad) the ratio of the fundamental sinusoid power to the total noise and distortion power. t otal harmonic distortion (thd) the ratio of the total power of the frst 9 harmonics to the power of the measured sinusoidal signal. spurious f ree dynamic r ange (sfdr) the ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal. figure 1. timing diagram 1
?2008 cadeka microcircuits llc www.cadeka.com 8 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a figure 2. timing diagram 2 table 1. timing parameters figure 3. typical interface circuit diagram description sym min typ max units conversion time t c t clk ns clk period t clk 40 ns clk high duty cycle t ch 40 50 60 % clk low duty cycle t cl 40 50 60 % clk to output delay (15pf load) t od 17 ns clk to dav t s 10 ns CDK1305
?2008 cadeka microcircuits llc www.cadeka.com 9 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a typical interface circuit very few external components are required to achieve the stated device performance. figure 2 shows the typical interface requirements when using the CDK1305 in normal circuit operation. the following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. power supplies and grounding cadeka suggests that both the digital and the analog supply voltages on the CDK1305 be derived from a single analog supply as shown in figure 2. a separate digital supply should be used for all interface circuitry. cadeka suggests using this power supply confguration to prevent a pos - sible latch-up condition on powerup. operating description the general architecture for the cmos adc is shown in the block diagram. the design contains 16 identical successive approximation adc sections, all operating in parallel, a 16-phase clock generator, an 11-bit 16:1 digital output multiplexer, correction logic, and a voltage reference gen - erator that provides common reference levels for each adc section. the high sample rate is achieved by using multiple sar adc sections in parallel, each of which samples the input signal in sequence. each adc uses 16 clock cycles to complete a conversion. the clock cycles are allocated as shown in table 2. table 2. clock cycles clock operation 1 reference zero sampling 2 auto-zero comparison 3 auto-calibrate comparison 4 input sample 5-15 11-bit sar conversion 16 data transfer the 16-phase clock, which is derived from the input clock, synchronizes these events. the timing signals for adjacent adc sections are shifted by one clock cycle so that the an - alog input is sampled on every cycle of the input clock by exactly one adc section. after 16 clock periods, the tim - ing cycle repeats. the latency from analog input sample to the corresponding digital output is 12 clock cycles. n since only 16 comparators are used, a huge power savings is realized. n the auto-zero operation is done using a closed loop system that uses multiple samples of the comparators response to a reference zero. n the auto-calibrate operation, which calibrates the gain of the msb reference and the lsb reference, is also done with a closed loop system. multiple samples of the gain error are integrated to produce a calibration voltage for each adc section. n capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. n the total input capacitance is very low since sections of the converter that are not sampling the signal are isolated from the input by transmission gates. voltage reference the cdk130 5 requires the use of a single external voltage reference for driving the high side of the reference ladder. it must be within the range of 3v to 5v. the lower side of the ladder is typically tied to agnd (0.0v), but can be run up to 2.0v with a second reference. the analog input voltage range will track the total voltage difference measured between the ladder sense lines, v rhs and v rls . force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. by using the confguration shown in figure 4, offset and gain errors of less than 2 lsb can be obtained. in cases where wider variations in offset and gain can be tolerated, v ref can be tied directly to v rhf , and agnd can be tied directly to v rlf as shown in figure 5. decouple force and sense lines to agnd with a 0.01f capacitor (chip cap preferred) to minimize high-frequency noise injection. if this simplifed confguration is used, the following considerations should be taken into account. the reference ladder circuit shown in figure 5 is a simplifed representation of the actual reference ladder with force and sense taps shown. due to the actual internal structure of the ladder, the voltage drop from v rhf to v rhs is not equivalent to the voltage drop from v rlf to v rls .
?2008 cadeka microcircuits llc www.cadeka.com 10 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a figure 4. ladder force/sense circuit figure 5. reference ladder circuit typically, the top side voltage drop for v rhf to v rhs will equal: v rhf C v rhs = 2.25 % of (v rhf C v rlf ) (typical) and the bottom side voltage drop for v rls to v rlf will equal: v rls C v rlf = 1.9 % of (v rhf C v rlf ) (typical) figure 5 shows an example of expected voltage drops for a specifc case. v ref of 4.0v is applied to v rhf , and v rlf is tied to agnd. a 90mv drop is seen at v rhs (= 3.91v), and a 75mv increase is seen at v rls (= 0.075v). analog input v in is the analog input. the input voltage range is from v rls to v rhs (typically 4.0v) and will scale proportionally with respect to the voltage reference. (see voltage refer - ence section.) the drive requirements for the analog inputs are very minimal when compared to most other converters due to the CDK1305 extremely low input capacitance of only 5pf and very high input resistance of 50k. the analog input should be protected through a series resistor and diode clamping circuit as shown in figure 7. figure 6. recommended input protection circuit calibration the cdk130 5 uses an auto-calibration scheme to ensure 10-bit accuracy over time and temperature. gain and offset errors are continually adjusted to 10-bit accuracy during device operation. this process is completely trans - parent to the user. upon powerup, the cdk130 5 begins its calibration algorithm. in order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10-bit lsb. since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. this results in a minimum calibration time upon powerup of 250s (for a 40mhz clock). once calibrated, the cdk130 5 remains calibrated over time and temperature. since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the cdk130 5 to remain in calibration.
?2008 cadeka microcircuits llc www.cadeka.com 11 data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a input protection all i/o pads are protected with an on-chip protection circuit shown in figure 6. this circuit provides esd robustness to 3.5kv and prevents latch-up under severe discharge conditions without degrading analog transition times. figure 7. on-chip protection circuit power supply sequencing considerations all logic inputs should be held low until power to the device has settled to the specifc tolerances. avoid power decoupling networks with large time constants that could delay vdd power to the device. clock input the CDK1305 is driven from a single-ended ttl-input clock. because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. digital outputs the digital outputs (d0Cd10) are driven by a sepa - rate supply (ovdd) ranging from +3 v to +5 v. this feature makes it possible to drive the CDK1305 ttl/cmos compatible outputs with the users logic system supply. the format of the output data (d0Cd9) is straight binary. (see table 3.) the outputs are latched on the rising edge of clk. these outputs can be switched into a tri-state mode by bringing en high. table 3. output data information analog input overrange d10 output code d9-d0 +f.s. + 1/2 lsb 1 1 1 1 1 1 1 1 1 1 1 +f.s. C1/2 lsb 0 1 1 1 1 1 1 1 1 1? +1/2 f.s. 0 ?? ???? ???? +1/2 lsb 0 0 0 0 0 0 0 0 0 0 ? 0.0v 0 0 0 0 0 0 0 0 0 0 0 (? indicates the fickering bit between logic 0 and 1.) overrange output the overrange output (d10) is an indication that the analog input signal has exceeded the positive fullscale input voltage by 1 lsb. when this condition occurs, d10 will switch to logic 1. all other data outputs (d0 to d9) will remain at logic 1 as long as d10 remains at logic 1. this feature makes it possible to include the CDK1305 in higher resolution systems. evaluation board the tbd evaluation board is available to aid designers in demonstrating the full performance of the CDK1305. this board includes a reference circuit, clock driver circuit, out - put data latches, and an on-board reconstruction of the digital data. an application note describing the operation of this board, as well as information on the testing of the CDK1305, is also available. contact the factory for price and availability.
for additional information regarding our products, please visit cadeka at: cadeka.com cadeka, the cadeka logo design, comlinear and the comlinear logo design are trademarks or registered trademarks of cadeka microcircuits llc. all other brand and product names may be trademarks of their respective companies. cadeka reserves the right to make changes to any products and services herein at any time without notice. cadeka does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by cadeka; nor does the purchase, lease, or use of a product or service from cadeka convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of cadeka or of third parties. copyright ?2008 by cadeka microcircuits llc. all rights reserved. cadeka headquarters loveland, colorado t: 970.663.5452 t: 877.663.5452 (toll free) data sheet CDK1305 10-bit, 40 msps 175mw a/d converter rev 1a ampl i f y t h e h uman exp eri e n c e mechanical dimensions soic-28 package tqfp-32 package a b c d e f j k l g i inches millimeters symbol min max min max a 0.346 0.362 8.80 9.20 b 0.272 0.280 6.90 7.10 c 0.346 0.362 8.80 9.20 d 0.272 0.280 6.90 7.10 e 0.031 typ 0.80 bsc f 0.012 0.016 0.30 0.40 g 0.053 0.057 1.35 1.45 h 0.002 0.006 0.05 0.15 i 0.037 0.041 0.95 1.05 j 0.007 0.17 k 7 0 0 7 l 0.020 0.030 0.50 0.75 h i inches millimeters symbol min max min max a 0.699 0.709 17.75 18.01 b 0.005 0.011 0.13 0.28 c d e 0.050 typ 1.27 bsc 0.018 typ 0.46 bsc f 0.090 g 0.031 0.039 0.79 0.99 0.0077 0.0083 0.20 0.21 0.096 2.29 2.44 h 0.396 0.416 10.06 10.57 i 0.286 0.292 7.26 7.42 f a b c d e g h i h

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